Digital logic circuits are increasingly used in all manner of consumer, governmental, industrial and other applications. Examples include personal computers, portable electronic devices such as personal organizers and calculators, electronic entertainment devices, and in control circuits for appliances, telephone switching systems, automobiles, aircraft, industrial control systems and other items of manufacture. Early digital logic was constructed out of discrete switching elements composed of individual bipolar transistors. With the invention of the bipolar integrated circuit, large numbers of individual switching elements could be combined on a single silicon substrate to create complete digital logic circuits such as inverters, NAND gates, NOR gates, flip-flops, adders, etc. However, the density of bipolar digital integrated circuits is limited by their high power consumption and the ability of packaging technology to dissipate the heat produced while the circuits are operating. The availability of metal oxide semiconductor (“MOS”) integrated circuits using field effect transistor (“FET”) switching elements significantly reduces the power consumption of digital logic and enables the construction of the high density, complex digital circuits used in current technology. The density and operating speed of MOS digital circuits are still limited by the need to dissipate the heat produced when the device is operating, and other factors, such as material costs, device yields and the like.
Digital logic integrated circuits constructed from bipolar or MOS devices do not function correctly under conditions of high heat or extreme environment. Many current digital integrated circuits are normally designed to operate at temperatures less than 100° C., while some that have been hardened for harsh environments are designed to operate at temperatures over 200° C. In conventional integrated circuits, the leakage current of the individual switching elements in the “off” state increases rapidly with temperature. As leakage current increases, the operating temperature of the device rises, the power consumed by the circuit increases, and the difficulty of discriminating the off state from the on state reduces circuit reliability. Conventional digital logic circuits may also short internally when subjected to extreme environments because they may generate electrical currents inside the semiconductor material. It is possible to manufacture integrated circuits with special devices and isolation techniques so that they remain operational when exposed to extreme environments, but the high cost of these devices limits their availability and practicality. In addition, such digital circuits exhibit timing differences from their normal counterparts, requiring additional design verification to add protection to an existing design.
Integrated circuits constructed from either bipolar or FET switching elements are volatile. They only maintain their internal logical state while power is applied to the device. When power is removed, the internal state is lost unless some type of non-volatile memory circuit, such as EEPROM (electrically erasable programmable read-only memory), is added internal or external to the device to maintain the logical state. Even if non-volatile memory is utilized to maintain the logical state, additional circuitry is necessary to transfer the digital logic state to the memory before power is lost, and to restore the state of the individual logic circuits when power is restored to the device. Alternative solutions to avoid losing information in volatile digital circuits, such as battery backup, also add cost and complexity to digital designs.
Important characteristics for logic circuits in an electronic device are low cost, high density, low power, and high speed. Conventional logic solutions are limited to silicon substrates, but logic circuits built on other substrates would allow logic devices to be integrated directly into many manufactured products in a single step, further reducing cost.
Various devices have been proposed that incorporate nanotubes to form non-volatile memory. For example, as disclosed in U.S. Pat. No. 6,919,592, a nanofabric may be patterned into ribbons, and the ribbons can be used as a component to create non-volatile electromechanical memory cells. The ribbon is electromechanically-deflectable in response to electrical stimulus of control traces and/or the ribbon. The deflected, physical state of the ribbon may be made to represent a corresponding information state. The deflected, physical state has non-volatile properties, meaning the ribbon retains its physical (and therefore informational) state even if power to the memory cell is removed. As disclosed in U.S. Pat. No. 6,911,682, entitled “Electromechanical Three-Trace Junction Devices,” three-trace architectures may be used for electromechanical memory cells, in which the two of the traces are electrodes to control the deflection of the ribbon.
The use of an electromechanical bi-stable device for digital information storage has also been suggested (See U.S. Pat. No. 4,979,149, entitled “Non-volatile Memory Device Including a Micro-Mechanical Storage Element”).
The creation and operation of bi-stable, nano-electro-mechanical switches based on carbon nanotubes (including mono-layers constructed thereof) and two metal terminals has been detailed in earlier patent applications having a common assignee as the present application, including U.S. Pat. Nos. 6,784,028; 6,835,591; 6,574,130; 6,643,165; 6,706,402; 6,919,592; 6,911,682; 6,924,538; 7,479,654 and 7,541,216; U.S. Patent Publication Nos. 2005-0062035, 2005-0035367, 2005-0036365, 2004-0181630; 2008-0012047; 2008-0158936; 2009-0243102 and 2010-0001267; and U.S. patent application Ser. Nos. 10/341,005; 10/341,055; 10/341,054; 10/341,130; 11/280,599 and 11/274,967; the contents of which are hereby incorporated by reference in their entireties (hereinafter and hereinbefore the “incorporated patent references”).
One application of bi-stable, two terminal nanotube switches is in non-volatile carbon nanotube (CNT) memory or nano random access memory (NRAM). An “ON or “1” state may be set with a current limited voltage pulse to set the switch as a memory bit to a low resistive state and an “OFF” or “0” state may be set with a non-current limited voltage pulse to set the switch to a high resistive state. One problem observed in the use of these switches as NRAM is that a first pulse used to turn an entire array of bits “OFF” may result in a significant number of bits turning “ON” to a very low resistive state. Due to the low currents that are available when using complementary metal-oxide-semiconductor (CMOS) chips, this can result in a situation where it is not possible to switch the switches “OFF” again, with the result that the switches are considered stuck. Since it is generally necessary to assure the workings and capacity of the memory, stuck switches represent defects in the NRAM memory, resulting in undesirably low memory device yields.
Accordingly, it is desirable to provide improved NRAM memory arrays that utilize two terminal carbon nanotube switches, particularly those having improved memory yields, as well as methods for making improved NRAM memory arrays.